Accelerated graphics port, commonly referred to as AGP, is a bus specification that was developed by Intel Corporation to provide graphics devices with faster access to main memory than the access speeds provided by the well-known peripheral control interconnect (PCI) bus specification, which was also developed by Intel Corporation. The PCI bus enables peripheral devices, such as, for example, keyboards, mice, printers and monitors to be connected to a central processing unit (CPU) and to operate a synchronously.
In computer graphics display systems, the need to provide the graphics device with direct access to the system main memory is especially important because graphics processing overhead, which is always a primary concern, can be reduced by providing the graphics device with direct access to the main memory. In these types of systems, the graphics device often is the only peripheral that is interconnected with the system CPU and with main memory. Therefore, there is often no need for a bus interface, such as the PCI interface, that is capable of communicating with several different types of peripherals. While the ability to communicate with several different types of peripherals provides obvious advantages, a direct, point-to-point connection between the main memory and a peripheral, such as a graphics device, provides faster access to the main memory because no intermediate processing is required to be performed by the bus interface to format the data for the particular peripheral that is accessing the main memory. AGP was developed in response to this need for a point-to-point interface between a graphics device and main memory that would allow faster access to main memory by the graphics device.
PCI typically operates at frequencies ranging from 33 MHz to 66 MHz with data transmitted on the rising edge of PCI clock. In an AGP system, data is transmitted on the rising and falling edges of a strobe. The strobe operates at frequencies ranging from 33 MHz to 66 MHz, resulting in a doubling of the data rate of a AGP interface system compared to a PCI system. In accordance with the AGP interface specification, the falling edge of strobe occurs in a known AGP clock cycle while the rising edge could occur in the same clock cycle as the rising edge or the subsequent cycle. This timing relationship complicates the task of synchronizing the received data with the AGP interface clock.
Currently, no satisfactory solution to this AGP synchronization problem has been developed. Accordingly, a need exists for a method and apparatus for synchronizing data received in an AGP interface.